553 Silly Mixer
553 : Silly Mixer
- Author: James Buchanan
- Description: A Silly Mixer or a silly weighted sum.(You deicde)
- GitHub repository
- Open in 3D viewer
- Clock: 10000000 Hz
How it works
Using 4 bit values and 3 bit weighted value coefficant, these valuers are mixed by using the Result = A1 * Gain1 + B1 * Gain2 relationship.
How to test
FPGA use required to input and examine output
External hardware
FPGA use required to input and examine output
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | ui_in[0] | uo_out[0] | uio_in[0] |
| 1 | ui_in[1] | uo_out[1] | uio_in[1] |
| 2 | ui_in[2] | uo_out[2] | uio_in[2] |
| 3 | ui_in[3] | uo_out[3] | uio_in[3] |
| 4 | ui_in[4] | uo_out[4] | uio_in[4] |
| 5 | ui_in[5] | uo_out[5] | uio_in[5] |
| 6 | ui_in[6] | uo_out[6] | uio_in[6] |
| 7 | ui_in[7] | uo_out[7] | uio_in[7] |