
There are multiple digital designs provided. The first one at the top is a four bit counter, which counts up to 1111 and triggers an output. The second design includes a +ve and -ve edge trigger logic. The third design is an LFSR for pseudo random number generator sequence. The last design has multiple pulse counters and trigger circuit, considered as a reservoir.
On-chip clock and external inputs could be connected and output ports are used to observe teh output.
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| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | IN0 | OUT0 | D0 |
| 1 | IN1 | OUT1 | D1 |
| 2 | IN2 | OUT2 | D2 |
| 3 | RST_N | OUT3 | D3 |
| 4 | OUT4 | D4 | |
| 5 | OUT5 | D5 | |
| 6 | OUT6 | D6 | |
| 7 | D7 |