132 4-Bit Charge-Redistribution SAR ADC Controller
132 : 4-Bit Charge-Redistribution SAR ADC Controller
- Author: Josue Olivos
- Description: Three selectable digital controllers for an external 4-bit charge-redistribution SAR ADC: clean, manually enabled Trojan, and automatically triggered Trojan designs.
- GitHub repository
- Open in 3D viewer
- Open in Tiny Tapeout Explorer
- Clock: 50000000 Hz
How it works
This project contains three selectable 4-bit SAR ADC controllers:
00– Clean controller01– Manual-Trojan controller10– Automatic-Trojan controller11– Clean/default
The controllers share a clock divider and comparator synchronizer. The selected controller drives an external capacitor DAC, sample switch, and comparator.
During each conversion, the SAR controller samples the input, tests each bit from MSB to LSB, reads the comparator, and stores the completed 4-bit result.
The live DAC-control code is available on uo_out[3:0], while the stable final ADC result is available on uio_out[3:0].
The manual Trojan is enabled with ui_in[3]. The automatic Trojan activates internally for 50 conversions after every 450 normal conversions. During an infected period, the physical DAC-control outputs are inverted.
Pin mapping
Inputs
ui_in[0]– Comparator outputui_in[2:1]– Design selectorui_in[3]– Manual Trojan enable
Outputs
uo_out[3:0]– Live DAC-control bitsuo_out[4]– Sample-switch controluo_out[7:5]– FSM debug stateuio_out[3:0]– Stable final ADC result
uio_oe[3:0] = 1111, configuring the lower four bidirectional pins as outputs.
How to test
Connect the external comparator to ui_in[0], the DAC-control outputs to the capacitor switches, and uo_out[4] to the sample switch.
Select the desired controller using ui_in[2:1], apply reset, and provide a known analog input and reference voltage.
Read the completed conversion from:
uio_out[3:0]
For the clean controller, the expected 4-bit result is approximately:
ADC code ≈ (VIN / VREF) × 15
To test the manual Trojan, select 01 and control it with ui_in[3].
To test the automatic Trojan, select 10 and observe the outputs over multiple conversions. A logic analyzer or oscilloscope is recommended for observing the Trojan behavior.
External hardware
- Binary-weighted capacitor array
- CD4066 or similar analog switches
- External comparator such as LM393
- Sample switch
- Comparator pull-up resistor
- Reference-voltage source
- Analog input source
- Decoupling capacitors
- Breadboard or custom PCB
- Oscilloscope, logic analyzer, or microcontroller
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Comparator output | Selected live DAC bit 0 - LSB | Final ADC result bit 0 - LSB |
| 1 | Design select bit 0 | Selected live DAC bit 1 | Final ADC result bit 1 |
| 2 | Design select bit 1 | Selected live DAC bit 2 | Final ADC result bit 2 |
| 3 | Manual Trojan enable | Selected live DAC bit 3 - MSB | Final ADC result bit 3 - MSB |
| 4 | Selected sample switch control | ||
| 5 | Selected FSM state bit 0 | ||
| 6 | Selected FSM state bit 1 | ||
| 7 | Selected FSM state bit 2 |