
This processor interfaces an integrated 3D BEOL physical wire mesh (omega_metal_grid_3d.gds) fabricated in the SkyWater 130nm metallization stack (met1 through met5) directly with standard-cell CMOS threshold inverters.
The metal mesh provides continuous analog potential relaxation across physical conductors. The state of these physical wires is quantized into digital logic levels that feed a runtime-programmable Boolean circuit DAG (Directed Acyclic Graph) to evaluate Circuit-SAT formulations directly in hardware.
rst_n low for 4 clock cycles, then bring high.uio_in[0] = 1.prog_op on ui[2:0], prog_a on ui[7:3], prog_b on uio[7:4], and toggling uio[1] (prog_we).prog_a with uio[1] = 0.uio_in[0] = 0) and assert uio[3] = 1 (grid_stable).uo_out[0] for SAT, uo_out[1] for UNSAT, and uo_out[7:3] for the evaluated physical tap states.| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | prog_op[0] | SAT | prog_en (1=prog, 0=run) |
| 1 | prog_op[1] | UNSAT | prog_we (write strobe) |
| 2 | prog_op[2] | DONE | unused |
| 3 | prog_a[0] | tap_out[0] | grid_stable (relaxation trigger) |
| 4 | prog_a[1] | tap_out[1] | prog_b[0] |
| 5 | prog_a[2] | tap_out[2] | prog_b[1] |
| 6 | prog_a[3] | tap_out[3] | prog_b[2] |
| 7 | prog_a[4] | tap_out[4] | prog_b[3] |