395 Hepiarisc with SPI flash

395 : Hepiarisc with SPI flash

Design render

How it works

This is an implementation of the HEPIARISC ISA used by HEPIA to teach basic CPU architecture. Here are a summary of the specs

You can find a customasm base file at customasm_sample.s

MMIO Periherals

TBD

How to test

You can compile a program with customasm, then flash the binary in big endian to the flash, and enjoy !

External hardware

A SPI flash, any that can be read with the sequence: [0x03, A[23:16], A[15:8], A[7:0], D0, D1]

TODO

  • test RAM
  • add GPIO peripheral
  • add SPI/I2C
  • add "bank switch instruction"
  • programmable IRQ timer (EN (either none, timer or ext IRQ), div 8-256, )

IO

#InputOutputBidirectional
0extflash_spi_misoproject_extflash_spi_sck
1irq_nproject_extflash_spi_mosi
2project_extflash_spi_cs
3
4GPI_0GPO_0GPIO_0
5GPI_1GPO_1GPIO_1
6GPI_2GPO_2GPIO_2
7GPI_3GPO_3GPIO_3

Chip location

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