234 IEEE Workshop Simple CPU
234 : IEEE Workshop Simple CPU
- Author: Hadjer Bouyahiaoui, Maria Debbaghi
- Description: 8-bit accumulator CPU using a real IHP 256x8 SRAM macro for data memory; multi-cycle to tolerate the macro's registered read latency
- GitHub repository
- Open in 3D viewer
- Open in Tiny Tapeout Explorer
- Clock: 5000000 Hz
Workshop Simple CPU
How it works
This project implements a small 8-bit accumulator CPU designed as an educational Tiny Tapeout project.
The CPU contains:
- A 4-bit program counter (PC), allowing up to 16 program instructions.
- A 16 × 8-bit program ROM implemented as synthesizable Verilog
caselogic. - A 16 × 8-bit data RAM used by load, store, arithmetic, and logic instructions.
- An 8-bit accumulator (ACC) used as the main working register.
- An ALU supporting addition, subtraction, AND, OR, pass-through, and decrement.
- A zero flag (Z) used by the conditional
JZinstruction. - An 8-bit input port and an 8-bit output port.
- A
haltedstatus output for observing when the CPU executesHLT.
The CPU uses an 8-bit instruction format:
7 4 3 0
+---------+---------+
| opcode | operand |
+---------+---------+
4 bits 4 bits
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | gpio_in[0] | gpio_out[0] | halted (output) |
| 1 | gpio_in[1] | gpio_out[1] | uart_tx (output) |
| 2 | gpio_in[2] | gpio_out[2] | |
| 3 | gpio_in[3] | gpio_out[3] | |
| 4 | gpio_in[4] | gpio_out[4] | |
| 5 | gpio_in[5] | gpio_out[5] | |
| 6 | gpio_in[6] | gpio_out[6] | |
| 7 | gpio_in[7] | gpio_out[7] |