357 Izhikevich event bridge (4 contexts)

357 : Izhikevich event bridge (4 contexts)

Design render

How it works

This project implements four independently stored fixed-point Izhikevich neuron contexts in a 3x2 Tiny Tapeout IHP slot. A single signed serial multiplier and control engine are time-multiplexed across the four contexts to minimize duplicated arithmetic.

Each neuron stores membrane voltage V, recovery state U, synaptic current, bias/current, parameters a/b/c/d, two signed synaptic weights, and two source identifiers. Source IDs can select prior-step recurrent spikes or one of four external digital spike inputs. A STEP command advances all four neurons once and returns the spike bitmap.

The external event inputs are digital logic signals. Analog neurons should be connected through external comparators, Schmitt receivers, or appropriate level-conditioning circuitry. The intended small-system configuration can use two of the four event inputs and route one selected output back to an analog neuron through the FPGA/external pulse or current interface.

How to test

Run the RTL test with:

cd test
pip install -r requirements.txt
make -B

The test checks reset state, the Tiny Tapeout bidirectional-pin direction mask, register write/readback, the four-context boundary, a full network STEP, and the resulting membrane-voltage update.

After hardening, copy the IHP unpowered gate-level netlist to test/gate_level_netlist.v and run:

make -B GATES=yes

External hardware

Intended system:

  • FPGA providing clock, packet transport, buffering, and larger network routing.
  • External comparator/level-conditioned spike sources from analog neurons.
  • Optional external DAC/current-pulse drivers controlled by the FPGA for feedback into analog neurons.

IO

#InputOutputBidirectional
0command_data[0]response_data[0]command_valid
1command_data[1]response_data[1]command_ready
2command_data[2]response_data[2]response_ready
3command_data[3]response_data[3]response_valid
4command_data[4]response_data[4]spike_in0
5command_data[5]response_data[5]spike_in1
6command_data[6]response_data[6]spike_in2
7command_data[7]response_data[7]spike_in3

Chip location

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