134 NanoV RV32E one-tile RISC-V processor
134 : NanoV RV32E one-tile RISC-V processor
- Author: Wai Ming Lee
- Description: One-tile NanoV RV32E core with external SPI RAM and minimal GPIO
- GitHub repository
- Open in 3D viewer
- Open in Tiny Tapeout Explorer
- Clock: 12000000 Hz
How it works
NanoV is a compact bit-serial RV32E RISC-V processor. It executes the retained base-integer operations over multiple clock cycles to reduce hardware area. The one-tile derivative keeps 16 architectural registers, the base ALU and shifter, branches and jumps, external SPI instruction/data memory, and minimal GPIO.
To target a 1x1 Tiny Tapeout footprint, this derivative removes two optional
features from synthesis:
- the multiply unit, because multiplication is outside base RV32E;
- the UART receiver/transmitter peripheral.
The memory-mapped peripherals are:
| Address | Operation |
|---|---|
0x10000000 |
Read or write the eight dedicated GPIO outputs |
0x10000004 |
Read the eight dedicated GPIO inputs |
Instructions and data reside in external SPI RAM. The SPI interface uses uio0
for MOSI, uio1 for chip select, uio2 for clock, uio3 for MISO, and uio7
for hold. The design does not include caches or on-chip program RAM.
Important inherited NanoV behavior:
x3/gpis fixed at0x00001000.x4/tpis fixed at0x10000000.- traps, interrupts,
ecall, andebreakare not implemented.
This is therefore a bare-metal RV32E processor, not a Linux-capable SoC.
How to test
From the repository root:
python3 -m venv .venv
. .venv/bin/activate
pip install -r test/requirements.txt
python scripts/verify_one_tile_contract.py
cd test
python make_test_mem.py test.mem
make clean
make
! grep failure results.xml
The 97-word self-checking program exercises representative RV32E register ALU,
immediate ALU, shifts, signed and unsigned comparisons, all branch conditions,
JAL, JALR, SPI-memory load/store, and GPIO input. It writes 0x01 after
boot, 0xA5 on success, or 0xEE on the first failed comparison.
External hardware
- An SPI RAM compatible with command
0x03reads and0x02writes, or a microcontroller emulating that interface - Optional LEDs or a seven-segment display on
uo[7:0] - A 12 MHz Tiny Tapeout clock
Attribution
The CPU and original Tiny Tapeout wrapper are by Michael Bell and are licensed
under Apache-2.0. Exact pinned revisions and derivative changes are recorded in
UPSTREAM.md. Retained but unsynthesized UART sources preserve their original
MIT license notices.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | GPIO input 0 | GPIO output 0 / segment a | SPI RAM MOSI |
| 1 | GPIO input 1 | GPIO output 1 / segment b | SPI RAM chip select, active low |
| 2 | GPIO input 2 | GPIO output 2 / segment c | SPI RAM clock |
| 3 | GPIO input 3 | GPIO output 3 / segment d | SPI RAM MISO |
| 4 | GPIO input 4 | GPIO output 4 / segment e | Unused |
| 5 | GPIO input 5 | GPIO output 5 / segment f | Unused |
| 6 | GPIO input 6 | GPIO output 6 / segment g | Unused |
| 7 | GPIO input 7 | GPIO output 7 / decimal point | SPI RAM HOLD, active low |