686 FP32 Math Unit
686 : FP32 Math Unit
- Author: Sai Kiran Ratna
- Description: FP32 Math evaluation mapped to hardware switches and 7-segment display.
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- Clock: 0 Hz
How it works
This chip contains a floating point adder which supports the single datatype and an HDL counter connected to seven segment display .. All the code is generated by HDL Coder [ MATLAB].
How to test
Use the switches to pass the different inputs and the output will be displayed on the seven segment display
External hardware
List external hardware used in your project (e.g. PMOD, LED display, etc), if any
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | Test Case Select [0] | Segment A | Unused |
| 1 | Test Case Select [1] | Segment B | Unused |
| 2 | Test Case Select [2] | Segment C | Unused |
| 3 | Display Nibble Select [0] | Segment D | Unused |
| 4 | Display Nibble Select [1] | Segment E | Unused |
| 5 | Display Nibble Select [2] | Segment F | Unused |
| 6 | Reset Counter (rst) | Segment G | Unused |
| 7 | Direction Control (dir) | Decimal Point (off) | Unused |