
We gratefully acknowledge the Center of Excellence (CoE) in Integrated Circuits and Systems (ICAS) and the Department of Electronics and Communication Engineering (ECE) for providing the necessary resources and guidance. Special thanks to Dr. H V Ravish Aradhya (HoD- ECE), Dr. K R Usha Rani (Associate Dean-PG), Dr. K. S. Geetha (Vice Principal) and Dr. K. N. Subramanya (Principal) for their constant encouragement and support in facilitating this Tiny Tapeout SKY26C submission.
An ultra-low-area, zero-RAM statistical co-processor implemented in Verilog. The design tracks baseline and volatility to classify time-series anomalies like drift, glitches, and stuck sensors in real-time.
The sentinel receives an 8-bit input data stream through ui_in[7:0].
The design combines a streaming median and MAD (Median Absolute Deviation) tracker with a Temporal Persistence Engine. It operates entirely without memory buffers, utilizing continuous digital feedback loops to distinguish between transient outliers and persistent baseline shifts.
The dynamically tracked baseline is output through uo_out[7:0], while the winning anomaly class (event code) is indicated by uio_out[2:0]. The wake signal on uio_out[3] indicates that a statistically significant event has occurred.
Apply an 8-bit signal to the input pins (ui_in). Set configuration pins uio_in[7:6] to 0.
The classification code is output on uio_out[2:0]:
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | raw_in[0] | baseline_out[0] | event_code[0] |
| 1 | raw_in[1] | baseline_out[1] | event_code[1] |
| 2 | raw_in[2] | baseline_out[2] | event_code[2] |
| 3 | raw_in[3] | baseline_out[3] | wake_cpu_int |
| 4 | raw_in[4] | baseline_out[4] | debug_fsm_0 |
| 5 | raw_in[5] | baseline_out[5] | debug_fsm_1 |
| 6 | raw_in[6] | baseline_out[6] | cfg_thresh_scale |
| 7 | raw_in[7] | baseline_out[7] | cfg_momentum_en |