289 LIF Neuron SNN :: Quicker, easier and cheaper to make your own chip!

289 : LIF Neuron SNN

Author: Virginia

Description: Two neuron leaky integrate and fire SNN accelerator

Clock: 100000000 Hz

How it works

This LIF-Neuron are two neurons that coexsist on a single tile using spiking neural networking on a synchronus design as shown below.
<img src="FinalDesign4.png" alt="Final Design 4 architecture" width="600">

This is done by each neuron having its own hardware but with a shared input and weight data leading to ultimatly have its own spike.

This LIF-Neuron design uses a 8-bit ui_in bus for input data and the uio_in pins as control signals.

To load the lower 8 bits of the neuron input, place the value on ui_in [7:0] and set uio_in [0] high for one clock cycle
To load the upper 8 bits of the neuron input, place the value on ui_in [7:0] and set uio_in [0] high for one clock cycle
To write a weight, place the weight address on a ui_in[7:4] and the 4 bit wight on ui_in[3:0]. Setup uio_in[2] high to enable the write.
To read a wight, place the read address on ui_in[3:0] and set uio_in[3] high.
To preform a neuron step, set uio_in[4] high. This will send the stored 16-bit input to the LIF neuron core.
Use uio_in[5] to select the output neurons:
- 0 selects neuron 1
- 1 selects neuron 2
the selected neurons output is provided on uo_out:
- uo_out[3:0] = 4 bit membrane potential
- uo_out[4] = spike output
- uo_out[7:5] = unused and set to 0
- this design uses an active-low reset through rst_n

How to test

This design is functionaly verified with Cocotb testbench that drives TinyTapeout pins and checks neuron outputs.

If a test passes you should see TEST=1 PASS=1 FAIL=0

External hardware

No external hardware is needed for this design.

#	Input	Output	Bidirectional
0	data[0]	v_mem_bit[0]	load_x_low
1	data[1]	v_mem_bit[1]	load_x_high
2	data[2]	v_mem_bit[2]	write_weight
3	data[3]	v_mem_bit[3]	read_weight
4	data[4]		step
5	data[5]		neuron_select
6	data[6]
7	data[7]

Input

Output

Bidirectional

data[0]

v_mem_bit[0]

load_x_low

data[1]

v_mem_bit[1]

load_x_high

data[2]

v_mem_bit[2]

write_weight

data[3]

v_mem_bit[3]

read_weight

data[4]

step

data[5]

neuron_select

data[6]

data[7]

Chip location

289 LIF Neuron SNN