899 Dual Port RAM
899 : Dual Port RAM
- Author: Veda Mouktika Boddanapalli
- Description: 8-bit 16-word dual-port RAM with arbitration and collision detect
- GitHub repository
- Open in 3D viewer
- Open in Tiny Tapeout Explorer
- Clock: 50000000 Hz
How it works
This design is an 8-bit, 16-word dual-port RAM with arbitration and write-collision detection, sized to fit a single Tiny Tapeout tile (1×1).
The Tiny Tapeout top module (tt_um_vedam_dual_port_ram) connects the chip's 24 user pins to the internal dual_port_ram_top core using a shared multiplexed bus:
PORT_SEL(ui[0]) selects Port A (0) or Port B (1)ALE_N,RD_N,WR_N,CS_Ncontrol address latch, read, write, and chip select (active low)AD0–AD7(uio[0:7]) carry address and data on the same 8-bit busCOLLISION,GRANT_A,GRANT_B(uo[0:2]) report arbitration status
Write sequence (per port):
- Assert
CS_Nlow,ALE_Nlow, drive address onAD[7:0] - Deassert
ALE_N, assertWR_Nlow, drive data onAD[7:0] - Deassert
WR_NandCS_N
Read sequence (per port):
- Assert
CS_Nlow,ALE_Nlow, drive address onAD[7:0] - Deassert
ALE_N, assertRD_Nlow - Read data from
AD[7:0](bus driven by the RAM) - Deassert
RD_NandCS_N
Both ports share one memory array. Writing the same address from both ports at the same time raises COLLISION.
How to test
Run the Cocotb tests locally:
cd test
pip install -r requirements.txt
make clean
make
The tests verify Port A write/read, Port B write/read, independent access at different addresses, and idle status.
On silicon (demo board), drive the pins above using the pinout in info.yaml at 50 MHz.
External hardware
None required. The design is tested through the Tiny Tapeout multiplexer pins (ui, uo, uio).
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | PORT_SEL | COLLISION | AD0 |
| 1 | ALE_N | GRANT_A | AD1 |
| 2 | RD_N | GRANT_B | AD2 |
| 3 | WR_N | AD3 | |
| 4 | CS_N | AD4 | |
| 5 | SLEEP | AD5 | |
| 6 | RETENTION | AD6 | |
| 7 | AD7 |