716 Reconfigurable mixed-precision 2x2 systolic MAC array
716 : Reconfigurable mixed-precision 2x2 systolic MAC array
- Author: Dilip C, Aneesh, Shylashree N, RV College of Engineering
- Description: A 2x2 weight-stationary systolic multiply-accumulate array with 4-bit/2-bit configurable precision and zero-operand skip.
- GitHub repository
- Open in 3D viewer
- Open in Tiny Tapeout Explorer
- Clock: 10000000 Hz
Credits
We gratefully acknowledge the Center of Excellence (CoE) in Integrated Circuits and Systems (ICAS) and the Department of Electronics and Communication Engineering (ECE) for providing the necessary resources and guidance.
Special thanks to Dr. H V Ravish Aradhya (HoD- ECE), Dr. K R Usha Rani (Associate Dean-PG), Dr. K. S. Geetha (Vice Principal) and Dr. K. N. Subramanya (Principal) for their constant encouragement and support in facilitating this Tiny Tapeout SKY26C submission.
Reconfigurable mixed-precision 2x2 systolic MAC array
How it works
A 2x2 weight-stationary systolic array of multiply-accumulate processing elements (PEs). Two 4-bit activation streams (one per row) enter from the west and shift eastward through registered PEs every clock cycle. Weights are preloaded once via a 4-pulse load sequence, one PE per pulse, then held stationary while activations stream through.
Each PE:
- Optionally masks its activation and stored weight down to 2 bits
(
precision_sel = 1) instead of the full 4 bits -- a cheap way to get a genuine precision switch without a second multiplier tree. - If the (masked) activation is zero, forces both multiplier operands to a constant zero instead of switching on a result that's guaranteed to be zero -- "zero-skip" via operand isolation, standing in for literal clock-tree gating.
- Otherwise computes
product = a_masked * w_maskedandpsum_out = psum_in + product. - Forwards its activation to the PE to its east (registered), and its partial sum to the PE to its south (registered) -- the systolic dataflow.
Column 0's partial sum (PE(1,0)'s output) and column 1's partial sum
(PE(1,1)'s output) can't both fit on the 8 uo_out pins at once, so they
alternate: column 0 on even cycles, column 1 on odd cycles, flagged by
uio_out[7] (col_id).
Known limitation
psum_out has no saturation logic -- two PEs' 8-bit products summed down a
column can in principle exceed 8 bits and wrap. Left out to keep the gate
count down for a 1-tile project; a saturating adder would be the natural
next addition.
How to test
- Reset the design (
rst_nlow for a few cycles, then high). - Load weights: for each of the 4 PEs in order
PE(0,0), PE(0,1), PE(1,0), PE(1,1), setuio_in[3:0]to the desired weight and pulseuio_in[4](weight_load) high for exactly one clock cycle. - Set
uio_in[5](precision_sel) to 0 for 4-bit mode or 1 for 2-bit mode. - Drive
ui_in[3:0]with the row-0 activation andui_in[7:4]with the row-1 activation each cycle. - After 4 cycles (pipeline fill),
uio_out[6](valid_out) goes high anduo_outalternates between column 0 and column 1's partial sum every cycle, indicated byuio_out[7](col_id).
External hardware
None -- purely digital, no external hardware required.
IO
| # | Input | Output | Bidirectional |
|---|---|---|---|
| 0 | act_row0[0] | psum_out[0] | weight_in[0] |
| 1 | act_row0[1] | psum_out[1] | weight_in[1] |
| 2 | act_row0[2] | psum_out[2] | weight_in[2] |
| 3 | act_row0[3] | psum_out[3] | weight_in[3] |
| 4 | act_row1[0] | psum_out[4] | weight_load |
| 5 | act_row1[1] | psum_out[5] | precision_sel |
| 6 | act_row1[2] | psum_out[6] | valid_out |
| 7 | act_row1[3] | psum_out[7] | col_id |